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Method of Fabricate Sub-Micron LDD FET

IP.com Disclosure Number: IPCOM000045826D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

Shepard, JF: AUTHOR

Abstract

Lightly doped drain field-effect transistor (LDD FET) Srtuctures require controlled doping of the N- regions. A method for producing a sub-micron LDD FET structure is described which incorporates a technique for obtaining good control of the N- region.

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Method of Fabricate Sub-Micron LDD FET

Lightly doped drain field-effect transistor (LDD FET) Srtuctures require controlled doping of the N- regions. A method for producing a sub-micron LDD FET structure is described which incorporates a technique for obtaining good control of the N- region.

The following process details that technique and begins after the formation of recessed oxide isolation (ROI). A layer of N+ polysilicon 10, and silicon dioxide 11 are formed over the ROI and exposed monocrystalline silicon layer 12. Lithography and etching are used to open the regions designated to be the gate, with lightly doped N- regions of the LDD FET being formed as shown in Fig. 1.

The exposed silicon surfaces are reoxidized in a low temperature steam, e.g., 800 degrees C, ambient so that about a 50- to 100-nanometer silicon dioxide layer 14 is produced on single crystal region. N+ polysilicon layer 10 plus Si0(2) layer 11 thickness is about 3 or 4 times more than the thickness of layer 14. Arsenic ions are implanted into layers 11, 14 using an energy of about 100 KeV such that all arsenic remains within the thin thermal silicon dioxide layers 11, 14, as shown by dashed line 15 in Fig. 2. The oxidizing step temperature is such that N+ source/drain regions 18 are formed by outdiffusion from N polysilicon layer
10.

Silicon dioxide layer 20 is blanket chemical vapor deposited over the Fig. 2 structure and reactive ion etched (RIE) down to the silicon surface. This produces...