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Monostable Circuit with Calibrated Width Pulse

IP.com Disclosure Number: IPCOM000045841D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Orengo, G: AUTHOR [+3]

Abstract

The circuit shown in the drawing generates a calibrated width pulse under the control of a logic circuit.

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Monostable Circuit with Calibrated Width Pulse

The circuit shown in the drawing generates a calibrated width pulse under the control of a logic circuit.

In the logic circuit, if the SET input is at a level lower than V1, current ICOMP flows in the collector path of transistor T1 and is reflected into the collector path of transistor T4, through a current mirror comprising transistors T3 and T4. Thus transistor T5 is saturated, which maintains capacitor C discharged.

If the SET input is at a level higher than V1, current ICOMP flows in the collector path of transistor T2 which activates comparator COMP. Transistor TS is OF,F and capacitor C begins to charge.

The base of transistor T7 is at potential VREF, fixed by resistor R and current in transistor T9.

During the charge period of capacitor C, this potential VREF is higher than the potential on the base of T6, and transistors T7 and T10 are conducting. The output voltage at output OUT is high.

When the voltage on the base of T6 reaches VREF, transistor T7 and T10 are OFF and the output level becomes low. The calibrated width pulse is given by the product of C times R.

Depending upon the application of this monostable circuit, the control logic may be comprised of a plurality of current switch logic circuits stacked between the current source ICOMP and the emitters of T6 and T7 for controlling the generation of the output pulse.

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