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Replacement of Deflective Control Store Routines

IP.com Disclosure Number: IPCOM000045845D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Schoettler, P: AUTHOR

Abstract

Control routines are stored in a control read-only storage (ROS) in the figure. For defective parts of this ROS, a replacement program is stored in the random-access memory (RAM). A marking storage (MS) and the ROS are addressed simultaneously and by the same address. The MS contains a one-bit storage element for each address. A "1" bit is stored in MS for each defective address in ROS, generating an output signal IS through an AND gate which also receives a read control signal. Signal IS interrupts the processor which determines the cause of the interruption by means of an interrupt handler (INT) and switches to the replacement program in RAM according to the address in an instruction counter (IC). The last instruction of the replacement program is a branch back to the next sequential instruction of the control routine.

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Replacement of Deflective Control Store Routines

Control routines are stored in a control read-only storage (ROS) in the figure. For defective parts of this ROS, a replacement program is stored in the random-access memory (RAM). A marking storage (MS) and the ROS are addressed simultaneously and by the same address. The MS contains a one-bit storage element for each address.

A "1" bit is stored in MS for each defective address in ROS, generating an output signal IS through an AND gate which also receives a read control signal. Signal IS interrupts the processor which determines the cause of the interruption by means of an interrupt handler (INT) and switches to the replacement program in RAM according to the address in an instruction counter (IC). The last instruction of the replacement program is a branch back to the next sequential instruction of the control routine.

By means of the MS, each ROS address can be indicated as defective and a replacement program started at each ROS address. Fixed jump addresses in ROS for handling defective parts are not required. RAM need not store an entire subroutine but only those parts that are defective. This facilitates using control ROSs that are slightly defective.

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