Browse Prior Art Database

Soft Clock Stop

IP.com Disclosure Number: IPCOM000045847D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 78K

Publishing Venue

IBM

Related People

Chilinski, H: AUTHOR [+4]

Abstract

In microprogram-controlled processors, there are several operation modes for program debugging. In addition to the run mode there is generally an instruction step mode (ISM) and an address compare mode (ACM). In the ISM, only one instruction is executed after actuation of the start key START. Subsequently, the processor status can be observed. In the ACM, actuation of START causes a number of instructions to be executed until the address in the control storage address register (CSAR) and the compare value in the compare address register (CA-REG) match, which is determined by comparer (COMP). Then, the processor status is again observed.

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Soft Clock Stop

In microprogram-controlled processors, there are several operation modes for program debugging. In addition to the run mode there is generally an instruction step mode (ISM) and an address compare mode (ACM). In the ISM, only one instruction is executed after actuation of the start key START. Subsequently, the processor status can be observed. In the ACM, actuation of START causes a number of instructions to be executed until the address in the control storage address register (CSAR) and the compare value in the compare address register (CA-REG) match, which is determined by comparer (COMP). Then, the processor status is again observed.

To ensure that only instructions corresponding to the selected mode are executed, it is necessary to stop instruction processing at the right time, which is normally done by deactivating the clock pulses. But this is problematical with some instructions, such as those keeping certain functional units busy beyond the last cycle time TL. Thus, for example, a store operation keeps the storage and its control busy while the last data received are stored. TL in the processor is reached, however, after the last data have been transmitted.

This makes it necessary, on the one hand, to discontinue TL, so that no further instructions are executed, and, on the other, to continue TL while data are written into storage.

To resolve this conflict, two types of clocks, a stop and a no-stop clock, have been generated so far. This leads to additional pin requirements both on the clock generation and the user side, particularly in data processing systems using, in addition to the central processor, one or several small processors for certain jobs, such as for controlling input/output functions. As a result, each of these processors must have its own operation modes for program debugging.

This problem can be overcome by instruction processing being no longer stopped by deactivating the clock pulses but by forcing a NO-operation (NOP) at the output of operation register (OP-REG). In such a case, the forced NOP appe...