Browse Prior Art Database

Integrated Three Terminal Led Photodetector

IP.com Disclosure Number: IPCOM000045849D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Matino, H: AUTHOR

Abstract

This article describes an integrated three-terminal light-emitting/photodetecting array structure in which a light-emitting junction is formed in a gate region of the FET-type photodetecting device. The structure does not require a sense amplifier since the structure produces an output signal level which is compatible with the logic circuit, such as TTL (transistor-transistor logic). The structure is particularly adaptable to a print/photodetector head for a facsimile terminal in which the head is used for both recording an image on a recording medium and reading or sensing an image or mark on the medium.

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Integrated Three Terminal Led Photodetector

This article describes an integrated three-terminal light- emitting/photodetecting array structure in which a light-emitting junction is formed in a gate region of the FET-type photodetecting device. The structure does not require a sense amplifier since the structure produces an output signal level which is compatible with the logic circuit, such as TTL (transistor-transistor logic). The structure is particularly adaptable to a print/photodetector head for a facsimile terminal in which the head is used for both recording an image on a recording medium and reading or sensing an image or mark on the medium.

The circuit diagram for reading or sensing an image or mark is shown in Fig.
1. It comprises a detector 1 and an amplifier 2, the output of which is connected to a register 3. The integrated FET structure is shown in Fig. 2. The structure includes a source region 8, a drain region 9 and a gate region which has a P type Ga(1-x)Al(x)As region 4 and an N type Ga(1-y) Al(y)As region 5. The regions 4 and 5 form light emitting junction. Light incident into the structure is detected at N type GaAs region 6 and/or P type GaAs region 7 in which a depletion region is formed during the detecting operation by an application of a proper bias voltage.

Fig. 3 shows a flip-flop circuit including cross-coupled FET devices. The flip- flop is triggered by an optical light input signal of an electrical input signal applied to terminal 10...