Browse Prior Art Database

Three State Device and Circuit Testing

IP.com Disclosure Number: IPCOM000045892D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 4 page(s) / 68K

Publishing Venue

IBM

Related People

Flaherty, RJ: AUTHOR [+2]

Abstract

Logic devices and circuits containing three-state or push-pull elements may have failure modes that are normally untestable. The present article shows a technique for providing complete testability of such circuits and devices without imposing performance or power consumption penalties. The approach shown also eliminates the possibility of damage to circuits during test.

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Three State Device and Circuit Testing

Logic devices and circuits containing three-state or push-pull elements may have failure modes that are normally untestable. The present article shows a technique for providing complete testability of such circuits and devices without imposing performance or power consumption penalties. The approach shown also eliminates the possibility of damage to circuits during test.

FET and bipolar digital circuits and particularly three-state devices, such as drivers, transfer gates and the like, are capable of achieving a high impedance state when defective and thereby contain circuit-failure modes which are not guaranteed to be tested in a complete functional test. The truth tables for testing such devices contain non-logical values which are neither 1 nor 0 either for good circuits or for defective ones. High impedance (Z) or high current (B) values are producible, and the unpredictable result in logic circuits fed by these devices may occur.

This article modifies the circuit elements themselves by including switchable load resistors controlled by separate test gates or switches in the final logic output of the element. These switches are included on the switch by incorporation into the circuit at the time they are designed. Additionally, the final drive transistors which supply the logical 1 and 0 values to the output point are provided with additional controlled switches in the + and - voltage supplies. These are designed in and built with the other elements on the chip.

The switchable load resistances change the Z state in the truth tables into logical 1 and 0 values that can be tested. A distinction can thus be observed between good and defective devices. The switchable power supply connections change the B value states in the truth tables into logical 1 or 0 states to allow distinction between good and defective devices in this mode of failure. The circuit behavior with the switches in their normal non-testing state is unaffected by these modifications.

Fig. 1A illustrates a typical three-state driver circuit for transferring data input on node 1 to a data output on node 2 at driven voltages between +V and -V, respectively. The enable line 3 in conjunction with data line 1 is applied through AND circuits 4 and 5 and the final output drivers 6 and 7 to provide the output on node 2. Various faults are indicated in Fig. 1A that may occur when one or more of these elements are blocked, shorted, or stuck in one condition or another. The truth table in Fig. 1B illustrates the output states that may be observed at node 2 in response to changes on the data and enable lines 1 and 3, respectively, in the presence of a number of potential faults 1 through 12 in the truth table.

It may be observed from Fig. 1B that a number of Z and B conditions exist for which a definitive test is not produced.

Fig. 2A illustrates a push-pull driver circuit together with its fault modes, and Fig. 2B shows the truth table f...