Browse Prior Art Database

Inhibiting Cache Loading

IP.com Disclosure Number: IPCOM000045921D
Original Publication Date: 1983-May-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 54K

Publishing Venue

IBM

Related People

Duke, AH: AUTHOR [+4]

Abstract

A peripheral storage hierarchy has a volatile cache backed by a plurality of retentive direct-access storage devices (DASDs). When the host is building a chain of peripheral commands for the storage hierarchy that involves addresses spread randomly across a large set of DASD storage tracks, or a large data set is to be transferred and transfers optimized to DASD, or the references in the chain of command consist of nothing but a series of data writes, then the cache is inhibited from being loaded by any command in the chain. The cache may contain data related to data transfers in the chain. Subsequent to the chain, all data in the cache that is pinned to the cache is updated from the DASD.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 3

Inhibiting Cache Loading

A peripheral storage hierarchy has a volatile cache backed by a plurality of retentive direct-access storage devices (DASDs). When the host is building a chain of peripheral commands for the storage hierarchy that involves addresses spread randomly across a large set of DASD storage tracks, or a large data set is to be transferred and transfers optimized to DASD, or the references in the chain of command consist of nothing but a series of data writes, then the cache is inhibited from being loaded by any command in the chain. The cache may contain data related to data transfers in the chain. Subsequent to the chain, all data in the cache that is pinned to the cache is updated from the DASD. If the last track referenced was modified, then the contents of the last track referenced are transmitted to cache and all data in the cache related to other tracks that were modified in the DASD are deleted.

Referring to the figure, switches Sl and S2 and stage control represent a memory controller for the storage hierarchy. Switches Sl and S2 are shown in the inhibit cache load mode. The host, in instituting a chain of commands, begins the chain with a mode setting DEFINE EXTENT command with inhibit cache load attributes set to the active condition. This attribute signifies to the storage hierarchy and its control that all references made by commands in the chain do not identify tracks being referenced as candidates for promotion to the cache. As such, all data transfers between the host and the storage hierarchy are directed by switch Sl to the addressed DASD, unless the data transfer relates to the current contents or allocation status of the cache; then the data transfer occurs with the cache.

Upon completion of the chain of commands having such an attribute, the promotion of data from DASD that was modified by the chain of commands or was accessed by the chain of commands limits what data is transferred from DASD to cache by the stage control. Certain data may be deleted from the cache. The first step, subsequent to the completion of the chain, requires the controller to examine the tracks that were written into in the DASD and compare such tracks with the cache for determining whether or not the data is pinned to the cache. If any such data is identified, then that data, as modified in DASD, is promoted to cache at A by the stage control. Following updating the pinned data, the control then examines the activity on the last track referenced (LTR) in the chain of commands. If it was written into, then the contents of the last track referenced in DASD are promoted at B to cache by stage control. Then, the control examines whether or not other DASD tracks were written into during the chain of command. If this was the case, then the data contents of the cache corresponding to s...