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Packaging Electrical Analysis Algorithms in a High-Level Language Environment

IP.com Disclosure Number: IPCOM000045927D
Original Publication Date: 1983-May-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 4 page(s) / 17K

Publishing Venue

IBM

Related People

Cook, RF: AUTHOR [+2]

Abstract

Earlier articles µ1,2Ù have described net resistance modelling algorithms used in a program for physical design verification of FET LSI chips.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 41% of the total text.

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Packaging Electrical Analysis Algorithms in a High-Level Language Environment

Earlier articles µ1,2Ù have described net resistance modelling algorithms used in a program for physical design verification of FET LSI chips.

This article describes methods by which these and other electrical checking routines can be packaged to facilitate their use in a high-- level language environment so that they can be applied to the analysis of any planar chip technology independent of mask level, database structure and net complexity.

The Resistance Modelling Algorithm

In the high-level language environment provided by LSl, shapes, which may have been derived from LSI chip mask data, can be symbolically represented by polygon variables µ3Ù. Contact shapes, for example, may be derived directly from a special mask level, calculated from the intersections of shapes on more than one level or obtained by any other methods. The conducting net to be modelled and its associated contacts are therefore set up by the application programmer (user) in two such LSl variables.

Typically, the polygon variable representing the net is a single element with multiple vertices and that representing the contacts consists of multiple rectangular elements. These two variables are supplied to the resistance modelling function.

This function performs a pre-analysis of the net pattern, subdividing it into wire-like branches and non-wire-like areas and inserting pseudo-contacts at the junctions of branches where a contact does not already exist and at a central point in non-wire-like areas to which all contacts which it contains are joined by branches. Calculations are then performed for each branch to determine resistance (assuming unit sheet resistivity), minimum width and perceived start/end contact width.

Each pseudo-contact generated is stored as a polygon element which is catenated to the contact variable set which was provided as input.

Four multi-element arithmetic sets whose bound is the number of net branches provide the results of the branch analysis. They contain the resistance, minimum width and perceived start/end contact width of each branch.

The branches are related to the contact polygon set (which by now includes pseudo-contacts) by two integer variables which contain the start and end contact index, respectively, for each branch. These two variables taken together contain the complete net connectivity information in terms of contacts and their relationships with branches.

These last six result variables can all be indexed by a notional branch number.

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Resistance modelling is run once only per net; the results represent an analysis of the complete net. The pre-analysis of the conducting net topology helps to avoid some of the performance and space problems (proportional to the square of the number of contacts) of other methods of resistance modelling which return a point-to-point resistance for every pair of contacts in a net.

However, it is n...