Browse Prior Art Database

Vertical Short Gate FET Structure

IP.com Disclosure Number: IPCOM000045954D
Original Publication Date: 1983-May-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Jackson, TN: AUTHOR

Abstract

A vertical short gate GaAs FET structure is constructed as shown in connection with Figs. l to 7.

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Vertical Short Gate FET Structure

A vertical short gate GaAs FET structure is constructed as shown in connection with Figs. l to 7.

Alloyed ohmic contacts are applied on both sides of an n or n/+/ GaAs structure.

A fine line lithography is employed to position a resist for an ion mill or etch operation to form the embossed region. The dimension W should typically be 0.1 - 0.75 mm.

A conformal coating is deposited by a process such as chemical vapor deposition. The coating may be of Si/3/N/4/ or SiO/2/.

The conformal coating is etched using an etching system with a degree of anisotropy to retain portions of the conformal coating on the sides of the embossed region.

The structure is next proton bombarded or implanted with oxygen or boron to form semi-insulating regions, after which the remainder of the conformal coating is removed to produce the structure of Fig. 5.

A gate metal is next deposited using a metallization system capable of giving deposition angles that position the gate adjacent the embossed region. This could be done, for example, by using an approximate point source at a distance and doing two depositions, one for each side.

A light isotropic etch forms the finished device structure by removing the metal from the sides of the embossed region. If desired, the gate metal can be contacted at some distance from the drain contact to reduce gate resistance. The extent of this gate contact and the other device dimensions are formed conventionally.

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