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Gate Model of Dynamic FET Networks

IP.com Disclosure Number: IPCOM000045968D
Original Publication Date: 1983-May-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 5 page(s) / 64K

Publishing Venue

IBM

Related People

Pfister, GF: AUTHOR

Abstract

Given an FET network consisting of nodes connected to FET transistors, suppose a node A has been connected to Vdd, and a node B to ground; and then they are disconnected from Vdd and ground, and connected to each other. The values they then take on depend on their relative capacitances, C_A and C_B, as follows: C_A JJ C_B both nodes become 1 C_A OO C_B both nodes become 0 C_A = C_B both nodes become "undefined", or an error has occurred.

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Gate Model of Dynamic FET Networks

Given an FET network consisting of nodes connected to FET transistors, suppose a node A has been connected to Vdd, and a node B to ground; and then they are disconnected from Vdd and ground, and connected to each other. The values they then take on depend on their relative capacitances, C_A and C_B, as follows: C_A JJ C_B both nodes become 1 C_A OO C_B both nodes become 0

C_A = C_B both nodes become "undefined", or an error has occurred.

This phenomenon is called charge sharing; FET networks making use of it are referred to as dynamic, rather than static. The algorithm presented below provides an approximate gate model of charge sharing in dynamic FET networks. A prior-art technique for this case produces the incorrect logic shown in Fig. 2. This technique modifies that logic to that shown in Fig. 3. The box labelled "CS" is defined here, and "actual value" is the next value taken on by the mode modelled by this logic.

While the amount of logic created by this technique is related to the square of the number of nodes which can share charge, it can be reduced to very few gates for common cases.

The algorithm proceeds in two stages:

1. Each segment is divided into sub-networks which

can potentially share charge with each other.

2. Logic is constructed for each sub-network to model

the effect of charge sharing on it.

These two steps are described below.

Charge sharing cannot occur with any node that is connected to Vdd or ground, by definition. This means that a node participates in charge sharing only when its M (memory) value function is l. Nodes whose M is known to be a constant 0 can thus never participate in charge sharing, and can be eliminated from consideration by applying the following procedure to each segment: 1. Mark Vdd and ground 2. For all nodes which have had value functions

created for them, perform the following procedure:

a. Mark all nodes which have M = constant 0.

b. Mark any node connected through a resistive

device to a marked node, iteratively, until

no new nodes can be marked.

3. If any unmarked node has not had value functions

created for it, create them now. Then perform the

procedure listed in 2 above on those nodes.

4. Mark all transistors with a transfer terminal

connected to a marked node.

5. Remove from the segment all marked nodes and

transistors.

1

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The result of the above will be a set of (possibly disconnected) sub-networks within which charge sharing can occur. Each such sub-- network will be called a charge-sharing sub-network (CSN). A gate description of charge sharing will be created for each CSN, but first the electrical characteristics of charge sharing are described.

The actual value produced by charge sharing is defined using conservation of charge. Let C(i) be the capacitance of each node i, and Q(i) be the charge initially on each node i. Then after charge sharing, a group of connected nodes will have the same voltage (V) defined by V = SUM(Q(...