Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Low-Cost Multilayer Substrate Packaging

IP.com Disclosure Number: IPCOM000045972D
Original Publication Date: 1983-May-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Anderson, GE: AUTHOR

Abstract

There is illustrated and described a packaging technique which provides for substrates of two technologies in the same package. In the figure, a unified package is shown. It comprises metalized ceramic substrate 2 having chips 4 attached thereto and multilayer glass cloth substrate 6. Substrate 6 may have standard components 8 attached thereto as well as chips 10. Substrate 6 also includes ground and voltage planes 12. Solder pins 14 connect substrates 2 and 6 to form a unified package.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Low-Cost Multilayer Substrate Packaging

There is illustrated and described a packaging technique which provides for substrates of two technologies in the same package. In the figure, a unified package is shown. It comprises metalized ceramic substrate 2 having chips 4 attached thereto and multilayer glass cloth substrate 6. Substrate 6 may have standard components 8 attached thereto as well as chips 10. Substrate 6 also includes ground and voltage planes 12. Solder pins 14 connect substrates 2 and 6 to form a unified package.

Since multilayer cards as well as metalized ceramic technologies can be joined in a single package, circuit design prospects are enhanced. Package design occurs in two phases. The primary phase is manufactured as a standard metalized ceramic substrate up to the pinning operation. The secondary phase is manufactured in panel form and milled to size. The type of component adds to be made dictate whether the adds occur prior to pin solder or at the chip attach stage. A further advantage is obtained using this technique since the circuit designer is allowed versatility in the choice of chip/component source.

1

Page 2 of 2

2

[This page contains 2 pictures or other non-text objects]