Browse Prior Art Database

PLA ELSE Clause Implementation

IP.com Disclosure Number: IPCOM000045994D
Original Publication Date: 1983-May-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Kraft, WR: AUTHOR [+4]

Abstract

A programmable logic array (PLA) construction is described wherein the ELSE condition is implemented using, at most, one word line, as opposed to many word lines.

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PLA ELSE Clause Implementation

A programmable logic array (PLA) construction is described wherein the ELSE condition is implemented using, at most, one word line, as opposed to many word lines.

A PLA can be used to simulate the IF-THEN-ELSE proposition frequently found in software programs. "IF" the AND array input A has a predetermined bit pattern, "THEN" the word line 1 is activated. "ELSE" the word line 2 is activated. This is accomplished by way of special logic located between the AND array and the OR array and represented by inverter circuit 3 and AND circuit 4. In other words, when the "THEN" word line l is not activated, the "ELSE" word line 2 is instead activated.

When the PLA is used as a finite-state control unit, the AND array input B indicates the state the PLA is in. The input A includes the data which the PLA uses to guide the control function. The AND array personalization pattern for the B input line are identical for both word line l and word line 2 so that the "ELSE" condition and the "IF-- THEN" condition fall within the same machine state. If the PLA is used in an application where the B input lines have no effect on the IF-- THEN-ELSE function, then the AND circuit 4 may be omitted and the output of the inverter circuit 3 connected directly to the "ELSE" word line 2.

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