Browse Prior Art Database

Wafer Packaging and Wiring Method

IP.com Disclosure Number: IPCOM000046012D
Original Publication Date: 1983-May-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Millham, EH: AUTHOR [+2]

Abstract

This article teaches a method whereby all chip pads on a wafer may be simultaneously reflowed to an interposer which can also be reflowed to a substrate to provide input-output connections to all functional chips on the wafer.

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Wafer Packaging and Wiring Method

This article teaches a method whereby all chip pads on a wafer may be simultaneously reflowed to an interposer which can also be reflowed to a substrate to provide input-output connections to all functional chips on the wafer.

Fig. 1 represents a side view of the completed assembly. The interposer 11 performs the function of connecting chip pads on the wafer 12 to mirror image pads on the substrate 13. Pins 14 on the substrate are used to connect the assembly to the next level package. The wafer is attached to a cold plate 15. The entire assembly is secured by frame 17 and may be hermetically sealed.

The interposer is constructed as shown in Fig. 2. Four identical glass plates 18 are masked, using the same mask (not shown) for producing the solder pads on the wafer, and etched so that a hole is created through the glass plates at every chip pad location.

The four identical plates are then aligned and held apart in pairs so that noble metal wires l9 can be inserted therethrough. These wires are crimped at each end. The void between the inner glass plates is then filled with epoxy 20 and allowed to cure, securing all wires in place. The crimps are ground off from both sides planarizing the wires, and the outer glass plates removed.

Fig. 3 shows the method of attaching the completed interposer 11 to the wafer 12. The interposer 11 is temporarily mounted in a jig 21 and properly secured. The wafer is placed on a hot chuck 22 and alig...