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LSSD Scan Path Truncated to Minimum Length for Testing

IP.com Disclosure Number: IPCOM000046015D
Original Publication Date: 1983-May-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 4 page(s) / 38K

Publishing Venue

IBM

Related People

Moser, JJ: AUTHOR

Abstract

A design technique called Level Sensitive Scan Design (LSSD) is commonly used today in the design of VLSI logic structures. One advantage of LSSD is in simplifying test generation by making each shift register latch (SRL) memory element a scannable test point, but one result of this is large test data volume since the data to be scanned in and out must accompany each test pattern.

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LSSD Scan Path Truncated to Minimum Length for Testing

BACKGROUND

A design technique called Level Sensitive Scan Design (LSSD) is commonly used today in the design of VLSI logic structures. One advantage of LSSD is in simplifying test generation by making each shift register latch (SRL) memory element a scannable test point, but one result of this is large test data volume since the data to be scanned in and out must accompany each test pattern.

Another technique called partitioning is used today to divide extremely large logic structures into several smaller "partitions" in order to simplify a particular phase of logic design. Partitioning was initially employed to circumvent storage limitations during test generation but is becoming more popular as a means of containing other phases of design, such as physical layout and design verification.

PROBLEM

The volume of test data affects directly the cost of testing which is becoming a significant factor in product costs. As product size continues to increase, the cost of testing will become more significant since test data tends to increase as the square of the size increases. The technique described below could reduce the test time significantly for future LSSD products which are partitioned especially those designed to Electronic Chip In Place Testing (ECIPT) Design Rules.

One feature of ECIPT is the ability to migrate test patterns which are generated to test the chip level package up to all higher levels of packages. The ECIPT rules provide this capability by utilizing LSSD SRL to control chip inputs and to monitor chip outputs. These SRL can either be within the chip itself or can be in the driving or driven chip. Several versions of ECIPT exist, and the specifics vary somewhat with each version.

For an ECIPT-designed multi-chip module, all the test patterns generated to test the individual chip can be applied to the module by utilizing SRL to control and monitor chip pads which are not accessible at the module pins. A card can be tested with module test patterns using SRL to control and monitor module pins not accessible at the card tabs. This technique is applicable to all package levels such that chip test patterns can be applied to the product at the system level.

SOLUTION

Testing a partitioned section of logic on an LSSD design requires scanning all SRLs even though only a small subset of the memory elements may be invoked in the particular partition of logic being tested. Test data can be significantly reduced if memory elements which are not involved can be bypassed. The figure shows conceptually how an LSSD shift register could be selectively shortened to optimize test time. The switches and wiring shown represent how the SRLs are

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connected in order to scan data in or out. In general, the test time required will be inversely proportional to the number of partitions, such that a structure divided into 10 equal partitions is test...