Browse Prior Art Database

Programmable Hardware Data Packing

IP.com Disclosure Number: IPCOM000046016D
Original Publication Date: 1983-May-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Anemojanis, E: AUTHOR

Abstract

This article describes apparatus that will generate in real time a reference data packing table which can reconstruct the total map at the host and the type and amount of data transferred to the CPU and host.

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Programmable Hardware Data Packing

This article describes apparatus that will generate in real time a reference data packing table which can reconstruct the total map at the host and the type and amount of data transferred to the CPU and host.

In addition, this feature is programmable and self adjusting to the prevailing failure mode within a product lot.

This is particularly designed for AC functional testing of wide data field devices.

The Fail Mode Memory 10, which could be a read-only memory, includes a SAR (storage address register) whose size is equal to the data field width of the device under test (DUT).

The data width of this memory depends on the number of comparisonfail modes desired. For example, if four fail modes are desired, this memory must be 4 bits wide and each data output is connected to a different counter.

The DUT error-checked output is the SAR of this memory; therefore, whenever the DUT output is of the programmed fail mode, the corresponding counter will be incremented. By the end of the test the four counters will hold numbers corresponding to the programmed failure modes. This information is transferred to the CPU at the end of the test.

The Reference Memory contains the compacted code of the DUT. The Code Generator is a read-only memory addressed by the outputs of the comparators (DI/DO = code outputs) The Reference Memory data out is formatted into 16-bit words prior to transfer to the CPU.

Data is usually transferred to the CPU by tr...