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Browse Prior Art Database

Programmable Partitioning Function for Memory Cell Map Buffers

IP.com Disclosure Number: IPCOM000046017D
Original Publication Date: 1983-May-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Anemojanis, E: AUTHOR

Abstract

This circuit can, under program control, sectionalize a large buffer. Based on the data of the status register, selection of particular segments is transferred to the CPU, thus greatly reducing the amount and type of data being transferred which enhances the throughput of the system, allows the partitioning of the pass/fail data, and transmits selective segments based on programmable length and limits.

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Programmable Partitioning Function for Memory Cell Map Buffers

This circuit can, under program control, sectionalize a large buffer. Based on the data of the status register, selection of particular segments is transferred to the CPU, thus greatly reducing the amount and type of data being transferred which enhances the throughput of the system, allows the partitioning of the pass/fail data, and transmits selective segments based on programmable length and limits.

An example will clarify the operation of the circuit shown in the figure. Assume that a one-megabit device (not shown) organized as 8 bits by 128 K addresses is being tested. This will be the size of the cell buffer required and the amount of data transferred to the CPU. With this circuit the device under test, can be divided into any number of equal segments, for example, 8K address segments. This value minus 1 will be loaded in the Section Address Number Register (SANR) from the Part Number Program (PNP) Register. The Section Fail Limit Register (SFLR) is loaded with the desired Fail Limit from PNP Register. The Section Address Counter (SAC) is loaded with the value of the SANR initially from the PNP Register. The Section Fail Counter (SFC) and Section Status Register (SSR) are reset.

As the PNP is executed, the Change of Address Lines from the Pattern Generator (PG) decrements the preset SAC. The fail input to the SFC is compared always with the output of the SFLR. When the SAC counts down, past zero...