Browse Prior Art Database

Memory Array Chip With Word Drivers on Bit Pitch

IP.com Disclosure Number: IPCOM000046018D
Original Publication Date: 1983-May-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Kilmer, CA: AUTHOR [+2]

Abstract

This memory array chip wiring technique enables increased chip density by using a second level of metal to interconnect word driver outputs to word lines, permitting word decoders to be physically placed at locations other than parallel to the word line pitch.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Memory Array Chip With Word Drivers on Bit Pitch

This memory array chip wiring technique enables increased chip density by using a second level of metal to interconnect word driver outputs to word lines, permitting word decoders to be physically placed at locations other than parallel to the word line pitch.

Multi-array memory chip layout designs in the past have used an "I"-type layout for array support circuits. In a typical array, the word line decoders and drivers are placed at the top/bottom of the arrays at the same pitch as the word lines. Bit decoders are placed between arrays at the same pitch as the bit lines.

Figs. 1 and 2 are alternative "U" and "H" layouts, respectively, which do not constrain the array width to the pitch of the word lines. In the "U" layout both word and bit decoders are placed at the sides of a pair of arrays on memory chip
10. Second level metallurgy 12 is used to interconnect the vertical word driver outputs to the vertical word lines in one or more arrays. A similar "H" layout is shown in Fig. 2 for a memory chip having four arrays.

1

Page 2 of 2

2

[This page contains 3 pictures or other non-text objects]