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Forming of Silicon Oxide Sidewall for Polysilicon Base Transistors

IP.com Disclosure Number: IPCOM000046045D
Original Publication Date: 1983-May-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 57K

Publishing Venue

IBM

Related People

Chu, SF: AUTHOR [+3]

Abstract

An important process parameter for polysilicon base transistors is the silicon dioxide sidewall thickness which determines the separationbetween the emitter and the extrinsic base regions, and, consequently,the doping levels at which these two regions intercept. Therefore, the current gain, the emitter-base diffusion capacitance, and the emitter-- base breakdown voltage are all dependent on this sidewall thickness. By controlling the sidewall thickness, it is possible not only to tighten the distribution of these parameters but also to improve them.

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Forming of Silicon Oxide Sidewall for Polysilicon Base Transistors

An important process parameter for polysilicon base transistors is the silicon dioxide sidewall thickness which determines the separationbetween the emitter and the extrinsic base regions, and, consequently,the doping levels at which these two regions intercept. Therefore, the current gain, the emitter-base diffusion capacitance, and the emitter-- base breakdown voltage are all dependent on this sidewall thickness. By controlling the sidewall thickness, it is possible not only to tighten the distribution of these parameters but also to improve them.

Two methods for forming the silicon dioxide sidewall by using low pressure chemical vapor deposition (LPCVD) polysilicon are particularly useful. Experiments have shown that the LPCVD polysilicon deposited at 625OEC using SiH/4/ provides excellent uniformity and coverage of the bipolar transistor topography. Upon thermal oxidation at about 800OEC, the polysilicon can be fully converted to silicon dioxide whose thickness satisfies the requirements for sidewalls. The processing steps are as follows:

1) After the emitter region is opened by reactive ion etching (RIE) down through polysilicon layer 11 and insulator layer 12 to the epitaxial layer 10, a 50 nm thermal silicon dioxide layer 14 is grown, as seen in Fig. 1.

2) Deposit polysilicon layer 16 in thickness of about 110 nm at 625OEC in Si//H/4/ LPCVD system, as shown by Fig. 2.

Thereafter, either of...