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Preventing Formation of Polysilicon Rails

IP.com Disclosure Number: IPCOM000046046D
Original Publication Date: 1983-May-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 58K

Publishing Venue

IBM

Related People

Jambotkar, CG: AUTHOR

Abstract

A method is described for preventing residues, or "rails", of polysilicon which often get left behind on wafers after patterns have been formed in a polysilicon layer using reactive ion etching (RIE).

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Preventing Formation of Polysilicon Rails

A method is described for preventing residues, or "rails", of polysilicon which often get left behind on wafers after patterns have been formed in a polysilicon layer using reactive ion etching (RIE).

In integrated circuit processes, a layer of polysilicon ("poly") is frequently deposited on wafers which already have some topography rather than flat surfaces. The topography is especially severe, as illustrated in Fig. 1, when recessed oxide regions 5 accompanied by the well-known "birds' beaks" have been formed prior to poly deposition. Reactive ion etching is commonly used for etching patterns in the poly layer 6. As shown at locations 10 in Fig. 2, even after overetching, "rails" of poly tend to remain behind birds' beaks and at other steps in the substrate topography. These rails remain as a consequence of the vertically directional nature of RIE. If these rails were allowed to remain through the end of wafer processing, they would create undesirable shorts in the integrated circuits. The state-of-the-art solution to this problem is to use either isotropic plasma etching or wet etching for a sufficiently long time to ensure complete removal of all poly rails 10 everywhere on the wafers. During this operation, sides of the regular poly patterns being exposed to the etchant also get appreciably etched. This introduces an additional variability in the dimensions of the poly patterns and also adversely impacts integrated circuit density.

A method is described below that will prevent the formation of the aforesaid poly rails and thus avoid the need for isotropic plasma or wet etching after the poly is patterned through RIE.

The preferred method consists of successive deposition of about 500 ~ thick Si/3/N/4/ 12 and a sufficiently thick layer of pyrolytic SiO/2/ 14 (about 4000 ~) on the wafers prior to poly deposition. The pyrolytic SiO/2/ l4 is then subjected to vertically directional RIE until the essential structure of Fig. 3 results. A selective etchant, such as CHF/3/, may be used for this...