Browse Prior Art Database

Simplified Isolation for an Integrated Circuit

IP.com Disclosure Number: IPCOM000046048D
Original Publication Date: 1983-May-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 39K

Publishing Venue

IBM

Related People

Abbas, SA: AUTHOR [+2]

Abstract

This process provides P+ substrate contact reach-through with a blanket subcollector as well as Pt Si Schottky barrier diodes. The isolation trench is filled with polyimide to minimize stress in the silicon, thereby improving product yield and leakage.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 54% of the total text.

Page 1 of 3

Simplified Isolation for an Integrated Circuit

This process provides P+ substrate contact reach-through with a blanket subcollector as well as Pt Si Schottky barrier diodes. The isolation trench is filled with polyimide to minimize stress in the silicon, thereby improving product yield and leakage.

The process proceeds as described in the following steps:

(1) The initial structure is a P- substrate 10 having a blanket Nsubcollector 11 and N- epitaxial layer 12 thereon. An epitaxial reoxidation silicon dioxide layer (not shown) is performed.

(2) Form the recess oxide isolation (ROI) l3 preferably substantially "bird's beak" free by any conventional approach. Do a N+ collector reach-through implant in a conventional manner to form N+ region l4.

(3) Mask and open the extrinsic base window.

(4) Chemically vapor deposit (CVD) polycrystalline silicon layer 15 for the extrinsic base. CVD silicon dioxide layer 16.

(5) Implant the polycrystalline silicon with boron before the CVD silicon dioxide layer 16, if the layer is thick; otherwise, use the CVD as screen oxide for implantation into layer 15. A separate screen silicon dioxide or silicon nitride step may be used here, if desired. A partial drive-in of the boron at this stage is an attractive option to ease the extrinsic-intrinsic base link-up problem.

(6) Use a resist mask 17 to reactive ion etch (RIE) the deep trench with the resist layer 17 itself as a mask or use the resist as a mask for RIE of silicon dioxide layer 16, as shown in Fig. 1, and silicon dioxide layer 16 as a mask for silicon RIE, as shown in Fig.
2. Strip the resist layer 17.

(7) Deposit a resist layer and mask again. RIE through the polycrystalline silicon layer 15 using a fiducial for end-point detectionat the single crystal sur...