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Single-Pass Three-State Driver Testing

IP.com Disclosure Number: IPCOM000046050D
Original Publication Date: 1983-May-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 40K

Publishing Venue

IBM

Related People

Cha, CW: AUTHOR [+3]

Abstract

A method is provided to achieve a full test of three-state drivers by effective single-pass testing using conventional tester hardware.

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Single-Pass Three-State Driver Testing

A method is provided to achieve a full test of three-state drivers by effective single-pass testing using conventional tester hardware.

Existing methods for testing three-state devices require two-pass testing. In the two-pass testing, one pass is employed to distinguish the high impedance state (H-state) from logical 1 and the second pass to reapply the entire set of functional test patterns to distinquish the H-state from logical 0.

The method described here achieves three-state driver testing in a single pass of application of functional test patterns employing a tester that can only distinguish two logic states, i.e., 0 and l. In this regard, the functional test pattern set is slightly larger in size than that required for testing on a tester with the hardware capabilities to distinguish three states, i.e., 0, 1 and H.

Before describing the method, which is characterized as the H- diag method, it is first necesary to define a few relevant conditionsand terminologies. A test pattern set is defined as having 0-detect capability if it distinguishes logic level 0 from logic level H, but not logic level l from logic level H, in accordance with the truth table (column A) set forth below. Similarly, a test pattern is defined as having l-detect capability if it distinguishes logic level 1 from logic level H, but not logic level 0 from logic level H, in accordance with the truth table (column B) set forth below. The generation of these test pattern sets may be accomplished by specifying the 0-detect option and the l detect option, respectively, to the simulator during test pattern generation and fault simulation.

The present H-diag methodology requires the users to employ "0"-- detect followed by "l"-detect option to generate a test data file (TDF) for any part number with three-state drivers. The users are also required to specify a pattern using flags that will force all three-state drivers on the device under test into H- state. This pattern will be employed on the tester set-up calibration to avoid accidental burn-out of the device under test.

In order to avoid accidental burn-out of the chip power supply wirings due to multiple orthogonal conditions during tester calibration, the set-up record should have the following sequence:

1) Set up power supplies.

2) Connect power supplies.

3) Calibrate all receivers and drivers except

three-state

drivers.

4) Force 1/0 on all primary inputs with special flags

as defined

by the pin function command.

5) cabibrate the three-state devices for V/1/ and V/0/

1

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