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Apparatus for Minimal Test/Sorting for Partial Good Categories

IP.com Disclosure Number: IPCOM000046055D
Original Publication Date: 1983-May-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Aichelmann, FJ: AUTHOR [+2]

Abstract

This is a technique that minimizes the sorting categories for partial good grouping. This is accomplished by incorporating additional on-- chip personalization logic to accomplish a common grouping of differently defective chips. The personalization logic makes the partially good chips appear to have bad bits at the same logical address regardless of their actual physical locations.

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Apparatus for Minimal Test/Sorting for Partial Good Categories

This is a technique that minimizes the sorting categories for partial good grouping. This is accomplished by incorporating additional on-- chip personalization logic to accomplish a common grouping of differently defective chips. The personalization logic makes the partially good chips appear to have bad bits at the same logical address regardless of their actual physical locations.

Fig. 1 depicts a typical block diagram of a chip with multiplexedaddressing. Included within this diagram is personalization logic on the high-order address which is used to reduce the partial good categories into a common part number.

Fig. 2 shows a single-bit example of the logic structure for the personalization logic included in Fig. l for a single address bit. Fig. 3 completes this example by depicting a specific method of personalizing the memory elements of Fig. 3. Fig. 4 describes the personalization table for a 2-bit address example with the defective regions forced into the highest address location.

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