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AND/OR Invert With Latch

IP.com Disclosure Number: IPCOM000046083D
Original Publication Date: 1983-May-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 59K

Publishing Venue

IBM

Related People

Puri, YK: AUTHOR [+2]

Abstract

Fig. 1 illustrates a conventional AND/OR invert circuit 1 having the load device 2 and the active devices 3, 4, 5 and 6 which have an output which is gated through the clocked transfer device 8 to the active device 10 of the latch 15. Transfer device 7 provides for an alternate latch input to device 10. The latch 15 includes the load device 9 and active device 10, whose output is connected by means of the transfer device 12 to the active device 14. A load device 13 and active device 14 serve as the output portion of the latch 15. The clocks driving the gates of devices 7, 8, 11 and 12 are so timed that the device 11 permits the latch input to be refreshed while devices 7 and 8 are "off;" and device 12 serves as a feed forward device during the time devices 7, 8 and 11 are "off." The problem with the circuit of Fig.

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AND/OR Invert With Latch

Fig. 1 illustrates a conventional AND/OR invert circuit 1 having the load device 2 and the active devices 3, 4, 5 and 6 which have an output which is gated through the clocked transfer device 8 to the active device 10 of the latch
15. Transfer device 7 provides for an alternate latch input to device 10. The latch 15 includes the load device 9 and active device 10, whose output is connected by means of the transfer device 12 to the active device 14. A load device 13 and active device 14 serve as the output portion of the latch 15. The clocks driving the gates of devices 7, 8, 11 and 12 are so timed that the device 11 permits the latch input to be refreshed while devices 7 and 8 are "off;" and device 12 serves as a feed forward device during the time devices 7, 8 and 11 are "off." The problem with the circuit of Fig. l is that the delay from the AOI inputs to point A of the latch 15 is the sum of delays caused by two load device nodes device 2 and device 9.

Fig. 2 illustrates the improved circuit. The circuit of Fig. 2 includes the load device 20 and the active devices 22, 24, 26 and 28 which carry out the AOI function. The input to devices 22, 24, 26 and 28 is clocked through the respective transfer devices 21, 23, 25 and 27. Alternately, an alternate latch input can be gated through the transfer devices 29 and 30. The output node for the AOI at the source for the load device 20 is connected through the transfer device 12 to the active device 14 of the output inverter comprised of the load device 13 and the active device 14. The inputs clocked through devices 21, 23, 25, 27 form an AOI function at point A. The clocks to devices 12 and (31, 32) function in the same manner as that of the Fig. 1 configuration. Note that the output of the latch is the inverse of the output for the latch in Fig. 1.

The improvement for the circuit shown...