Browse Prior Art Database

Multishared Data Bus

IP.com Disclosure Number: IPCOM000046094D
Original Publication Date: 1983-May-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Chan, SK: AUTHOR [+3]

Abstract

The bus design disclosed in the article in the IBM Technical DisclosureBulletin 24, 1861 (September l98l) has one bus to a central processor (CP). If the service processor tried to use the bus for another purpose, a CP could not stop, then the condition was catastrophic.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Multishared Data Bus

The bus design disclosed in the article in the IBM Technical DisclosureBulletin 24, 1861 (September l98l) has one bus to a central processor (CP). If the service processor tried to use the bus for another purpose, a CP could not stop, then the condition was catastrophic.

Prior to the initiation of data transfer over the common bus, fence registers are loaded with control information to isolate one of the two units from the use of the shared bus. This allows one bus to be selectively used by (in this case) two users without interfering with each other.

The following shows the old and new sequences for the transfer of data on the shared bus.

(Image Omitted)

1

Page 2 of 2

2

[This page contains 5 pictures or other non-text objects]