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Activity Detection Circuit Using FET Technology

IP.com Disclosure Number: IPCOM000046100D
Original Publication Date: 1983-May-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 37K

Publishing Venue

IBM

Related People

Cranford, HC: AUTHOR [+2]

Abstract

A variety of data communications networks and elements require circuits for detecting the presence or absence of data transmission on a communications line or medium. Particularly, it is important to detect the presence of activity or its absence in order to detect failures at those points in the communications system. Failures can produce any level of DC signal on the input to an activity detection circuit and, hence, a requirement is to detect the fact that transitions have ceased in a fashion insensitive to DC input. The threshold detector circuit of the present disclosure avoids the problems inherent in a variety of prior designs, is insensitive to DC input, and has a sensitive threshold that provides an output when input signals have ceased.

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Activity Detection Circuit Using FET Technology

A variety of data communications networks and elements require circuits for detecting the presence or absence of data transmission on a communications line or medium. Particularly, it is important to detect the presence of activity or its absence in order to detect failures at those points in the communications system. Failures can produce any level of DC signal on the input to an activity detection circuit and, hence, a requirement is to detect the fact that transitions have ceased in a fashion insensitive to DC input. The threshold detector circuit of the present disclosure avoids the problems inherent in a variety of prior designs, is insensitive to DC input, and has a sensitive threshold that provides an output when input signals have ceased.

The figure illustrates the input pulse train being applied to the gate of a depletion-mode FET device 1. This device has its drain connected to its source, as schematically shown, so that it serves as an input isolation capacitor to block DC voltages. The depletion-mode FET 2 is used as a current limiter so that a preferred DC bias level is established at node A. The current through device 2 is chosen by selecting the area and width0-to-length ratio of device 2 such that node A will be approximately a short channel threshold voltage of ground when no signal activity is present. This is established by device 3 connected as shown with the gate voltage at node A. Device 3 will conduct for voltage at node A greater than the threshold voltage of device 3 which is made as a short channel FET. Thus, the voltage at node A need only be slightly greater than the enhancement device threshold voltage. The node A voltage is also connected to the gate of the enhancement-mode device 5. This FET is given a long channel where its length is approximately greater than or equal to 10 microns, for example. Its FET threshold will be greater by approximately 400 millivolts in capacitive FET technologies than that of device 3. Consequently, when no input transitions are present, node B will be established at approximately the input supply voltage +V by the depletion-- mode device 4 since device 5 will be off. However, each positive transition of the input will cause node A to be positive by capacitive coupling through device 1. Whenever the waveform at node A is repetitive, which is the case as long as there is activity present in the communication system (not shown) and providing that the capacitance of device 1 is sufficiently large in comparison to the total capacitance at node A, the voltage at node A will be pulsed positively at each input positive transition. These pulses will turn the device 5 on momentarily provided that the approximately 400-millivolt threshold is attained. Turning device 5 on momentarily will partially discharge the capacitance C/x/, shown as capacitor 6, and will lower the voltage at node B. The voltage at node B is selected to be above...