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Tip-Point Decoder Gate With Improved Margins

IP.com Disclosure Number: IPCOM000046102D
Original Publication Date: 1983-Jun-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Beha, H: AUTHOR [+2]

Abstract

In self-resetting decoder gates employed in Josephson memory designs undesirable multiple switching occurs because the gate resets after the fast transfer of its gate current into the output loop into the zero- voltage state while the input control current is still present. It is proposed to employ an asymmetric 2-junction tip-point interferometer which is damped such that the resulting change in the switching characteristic eliminates the occurrence of multiple switching.

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Tip-Point Decoder Gate With Improved Margins

In self-resetting decoder gates employed in Josephson memory designs undesirable multiple switching occurs because the gate resets after the fast transfer of its gate current into the output loop into the zero- voltage state while the input control current is still present. It is proposed to employ an asymmetric 2-junction tip-point interferometer which is damped such that the resulting change in the switching characteristic eliminates the occurrence of multiple switching.

Figs. 1 and 2, respectively, show the basic decoder circuit and the IG/IIN characteristic of an asymmetric 2-junction Josephson interferometer serving as a gate device. The dotted curves (A, B) represent possible current trajectories of the dynamic operation point of the gate. The gate may reset while in the 1-mode. When the current trajectory (A) crosses the mode boundary of the l-mode below the critical point CP, the gate returns to its initial state in the 0-mode without voltage transition. If, however, the current trajectory (B) crosses above CP, a voltage transition occurs and the gate produces an undesired second output pulse.

Figs. 3 and 4, respectively, show the proposed decoder circuit with damped decoder gate and the resulting IG/IIN characteristic. The proposed circuit differs from the circuit illustrated in Fig. 1 in that

1) the gate interferometer provides for a

well-defined critical point CP0 at the tip-point of the

0-mode curve whereby...