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Phase-Locked Loop Circuitry Comprising a Watchdog Circuit for Instability Suppression

IP.com Disclosure Number: IPCOM000046104D
Original Publication Date: 1983-Jun-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 56K

Publishing Venue

IBM

Related People

Keller, H: AUTHOR [+2]

Abstract

A phase-locked loop (PLL) circuit arrangement is suggested which is extremely stable in operation and is insensitive to timing instabilities in the received data stream due to an additional "watchdog" circuit which detects such instabilities and raises a corrective control signal if they exceed a given limit. This PLL circuitry is particularly suited for ring communication systems in which access to the transmission medium is regulated by a circulating token.

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Phase-Locked Loop Circuitry Comprising a Watchdog Circuit for Instability Suppression

A phase-locked loop (PLL) circuit arrangement is suggested which is extremely stable in operation and is insensitive to timing instabilities in the received data stream due to an additional "watchdog" circuit which detects such instabilities and raises a corrective control signal if they exceed a given limit. This PLL circuitry is particularly suited for ring communication systems in which access to the transmission medium is regulated by a circulating token.

Instabilities that tend to disturb PLL operation may be caused, e.g., by strong bursts of noise, by extended relay bouncing, or by the transfer of the ring monitor function from a failing station to another station.

The suggested PLL circuitry is shown in the drawing. Incoming data signals are forwarded from a receiver l0 to a transition detector ll which issues an output pulse on line l2 for each signal level transition. A phase detector l3 compares the resulting pulse signal to the PLL output signal fl and, in case of phase deviation, issues an UP or DOWN (U/D) signal which is transferred through multiplexer l4 to charge pumps and loop filter 15, e.g., current sources, which comprise a loop filter issuing a control voltage depending on the detected phase error. Voltage- controlled oscillator (VCO) 16 furnishes an output signal f1 on line 17 which is controlled in frequency and phase by the output signal of charge pumps and loop filter 15.

For initial frequency acquisition, a frequency and phase detector 18 is provided which receives a basic frequency signal f0 from a local quartz oscillator 19 and the VCO output signal f1. It also issues an UP or DOWN control signal through multiplexer 14 to charge pumps and loop filter 15, to change VCO output f1 until it is equal to f0.

To avoid mutual disturbance between fast frequency acquisition by detector 18 and slow but very exact phase correction by detector 13, they operate mutually exclusively under control of phase comparator 20 and lock detector 21. As long as phase comparator 20 indicates an out-of=phase condition between f1 and the received data, lock detector 21 and gate 22 control multiplexer 14 to transfer the UP/DOWN signal from detector 18 for changing the VCO output f1 to f0. When phase comparator 20 indicates an in-phase condition, lock detector 21, which has a certain inertia, i.e., an integrating effect, will control through gate 22...