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Browse Prior Art Database

Simplified Trench Planarization Process

IP.com Disclosure Number: IPCOM000046112D
Original Publication Date: 1983-Jun-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Ho, CW: AUTHOR [+2]

Abstract

This simplified trench planarization process (STPP) is a process for VLSI chip packaging. It provides a simple and clean process for fabrication of planar structures for thin film packaging. The STPP is described as follows:

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Simplified Trench Planarization Process

This simplified trench planarization process (STPP) is a process for VLSI chip packaging. It provides a simple and clean process for fabrication of planar structures for thin film packaging. The STPP is described as follows:

(1) Spin and cure polyimide P onto a substrate S

coated with metal M1 (Fig. 1). (2) Deposit a second dielectric D, e.g., SiOx, SiNx, etc., which also serves as an etching mask for the polyimide

(Fig. 1). (3) Form a pattern on a resist layer R1 by standard

lithographical resist patterning, leaving opening U

(Fig. 1). (4) Open features through opening U in dielectric D and

polyimide P by ion beam etching (or reactive ion

etching) to make a trench T (Fig. 2). (5) Employ in situ ion beam cleaning (ion milling) of the features by tilting (to change the angle of ion

incidence) and rotating the sample. (6) Deposit metallurgy (M2), e.g., Cr-Cu-Cr, by E-beam evaporation (Fig. 3). (7) Employ a short etch (dry or wet) to remove possible sidewall coverage which can also separate the metal in

trench T with respect to the rest of the undesired top

metallurgy M2 . (8) Apply resist R2 and try to planarize it so that a

significant difference in the thicknesses of the resist

inside and outside of the etched features is obtained

(Fig. 3). (9) The resist R2 is then given a blanket exposure of the

light source in a controlled dosage so that after

development only the surfaces of the undesired top

metallurgy M2 are completel...