Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Josephson-Semiconductor Interface Circuit

IP.com Disclosure Number: IPCOM000046118D
Original Publication Date: 1983-Jun-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 54K

Publishing Venue

IBM

Related People

Tsui, F: AUTHOR

Abstract

Interface circuitry, comprising signal form converters, single pulse delimiters and gate-and-latch circuits, provides bidirectional signal transfer between room-temperature semiconductor circuits and cryogenictemperature Josephson junction circuits.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 55% of the total text.

Page 1 of 3

Josephson-Semiconductor Interface Circuit

Interface circuitry, comprising signal form converters, single pulse delimiters and gate-and-latch circuits, provides bidirectional signal transfer between room- temperature semiconductor circuits and cryogenictemperature Josephson junction circuits.

A Josephson system operates in a low temperature (LT) enclosure, whereas the "external world" is at room temperature (RT). Communications between them traverse an RT/LT interface, which marks the boundary between two different circuit technologies: the semiconductor and the Josephson. On the RT side, there are semiconductor interface circuits (IFCSC); on the LT side, there are Josephson interface circuits (IFCJ).

Since the Josephson "latching-logic" circuits operate with an AC power supply, the signal-forms in the LT domain are basically different from those in the RT semiconductor domain. Also, there is a fundamental need for cycle-timing synchronization between the two domains for each I/O transfer across the interface. The two domains are independent and cannot be continuously synchronized. The LT domain is much faster; it may actually be necessary to slow the rise time to reduce crosstalk in cable connections.

The interface circuitry (Fig. l) has the basic structure of nD signal-form converters (SFC), single-pulse delimiters(s) (SPD), and nD gate-and-latch circuits (GL). For either direction of I/O transfer, the IFC comprises: for each incoming data signal, an SFC;

for each incoming control signal, an SFC and, in addition,

an SPD; and

for each incoming data line, a GL.

A form of implementation for IFCJ is shown in Fig. 2. The SFCJ is a simple OR-like circuit with only one input used. The SPDJ consis...