Browse Prior Art Database

Monitor for a Communication Linkage Using Sna/Sdlc

IP.com Disclosure Number: IPCOM000046135D
Original Publication Date: 1983-Jun-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Olson, GP: AUTHOR

Abstract

The present system relates to the monitoring of the communication linkage between data processing systems using IBM SNA (Systems Network Architecture) and SDLC (Synchronous Data Link Communication). With reference to the figure, the programmed tester is utilized to provide on-line monitoring of the communication linkage. The base line repeater card provides data, address, sync, data direction and data ready input to a parity generator circuit. It also includes a pair of driver-receiver units for communication respectively with a host and the unit or box under test. The present system utilizes time stamp addition features. Handshake logic is provided between the programmed tester and the repeater card. This handshake logic is required in order for the programmed tester to be operative.

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Monitor for a Communication Linkage Using Sna/Sdlc

The present system relates to the monitoring of the communication linkage between data processing systems using IBM SNA (Systems Network Architecture) and SDLC (Synchronous Data Link Communication). With reference to the figure, the programmed tester is utilized to provide on-line monitoring of the communication linkage. The base line repeater card provides data, address, sync, data direction and data ready input to a parity generator circuit. It also includes a pair of driver-receiver units for communication respectively with a host and the unit or box under test. The present system utilizes time stamp addition features. Handshake logic is provided between the programmed tester and the repeater card. This handshake logic is required in order for the programmed tester to be operative. The parity generator circuit will generate even parity over the l6 bits of incoming data. A "parity bad" bit line is provided between the parity generator and the programmed tester. The time stamp circuit is a 28-bit counter that runs at one microsecond intervals to give a maximum time of over 268 seconds. Signals from the repeater card are used to reset, count, and save the value for subsequent sampling by the programmed tester

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