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Enhanced State Sequencer for Sequential Logic Array

IP.com Disclosure Number: IPCOM000046149D
Original Publication Date: 1983-Jun-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 4 page(s) / 49K

Publishing Venue

IBM

Related People

Davis, GT: AUTHOR

Abstract

Additional functions are provided for a Sequential Logic Array (SLA), such as breaking up product terms into smaller, faster mini-terms, masking unused I/O groups in each product term, inverting product terms, organizing control words in RAM (random-access memory) to optimize performance and adding a two-level latch for sequencing control words to optimize performance.

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Enhanced State Sequencer for Sequential Logic Array

Additional functions are provided for a Sequential Logic Array (SLA), such as breaking up product terms into smaller, faster mini-terms, masking unused I/O groups in each product term, inverting product terms, organizing control words in RAM (random-access memory) to optimize performance and adding a two-level latch for sequencing control words to optimize performance.

The Sequencial Logic Array is a circuit which simulates a Programmable Logic Array (PLA) structure using standard memory modules, by solving product terms one at a time instead of all at once. This is an enhanced version of the U.S. Patent 4,357,678. Control of the sequence of product terms is accomplished by a State Sequencer. A block diagram of this circuit is shown in Fig. 1. A RAM array la, lb, organized as 4096 x 18 bits, is initialized with all data necessary to perform this task by data received from the microprocessor through buffers 2 and 3 with memory address controlled by addresses in buffers 4 and 5.

Fig. 2 illustrates the functions of each bit position in the two words serving to select the next product term. These bit positions are designated D0-Dl5 in the first word and D0'-Dl5' in the second word. Positions D0-D3 and D12-D15 for word 1 and D0'-D3' and D12'-D15' for word 2 are derived from RAM 1a. Positions D4-D11 and D4'-D11' are derived from Ram 1b. The 18 bits in each word consist of 16 data bits and 2 parity bits (l for each 8-bit byte). Of the 16 data bits, bits 0, 1 and 3-11 define the next address to be accessed, bits 12 through

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and defines the product term to be executed next if the current product term in registers 10, 12 and logic 11 is false. The parity bits are entered in parity check blocks 6 and 7. The second word, when accessed, is temporarily held at the outputs of RAMs 1a, 1b and transferred to registers 8 and 9 (and parity check blocks 6 and 7) only if the current product term is true. The second word defines the product term to be executed next if the current product term is true. (Actually, if the first input memory cycle of a product term is false, the second word is not needed and the sequencer jumps immediately to the next product term as defined in the first word.)

Latch Registers 8 and 9 will hold the first word from memory until the input cycles of the product term are completed. If the current product term turns out to be false, then the first word which is being held in Latch Registers 8 and 9 will be transferred to Latch Registers l0 and 12 to generate the address for the next product term with the aid of Logic block 11. Once a product term is determined to be true, then the second word out of RAM, which is held at the RAM outputs 1a and 1b, is then loaded into the Latch Registers 8 and 9. Then at the end of the output cycles, which is also the determination of the current product term, the contents of those latches will be loaded into Latch Registers 10 a...