Browse Prior Art Database

Microprocessor System Using SLA Devices As Smart Peripherals

IP.com Disclosure Number: IPCOM000046150D
Original Publication Date: 1983-Jun-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 64K

Publishing Venue

IBM

Related People

Davis, GT: AUTHOR

Abstract

Apparatus is described that provides an interface between Sequential Logic Array (SLA) structures and a communications link to implement a systems solution. Additional functions (timers, registers, arithmetics, etc.) as well as diagnostics are provided.

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Microprocessor System Using SLA Devices As Smart Peripherals

Apparatus is described that provides an interface between Sequential Logic Array (SLA) structures and a communications link to implement a systems solution. Additional functions (timers, registers, arithmetics, etc.) as well as diagnostics are provided.

The microcontroller section of the SLA Controller provides the basic interface between the logic array section and the communication link interface. It interprets and executes commands from each of these functions, and controls data transfers between them. It also provides RAS (reliability, availability, serviceability) aids, such as power on diagnostics and error monitoring, and executes a group of diagnostic commands which can be generated by the host IBM Series/1.

The microcontroller section, illustrated in the figure, includes a microprocessor 1 which handles the four SLA partitions 11-14 as smart I/O controllers. Each of the blocks 11-14, as well as block 7, includes a RAM (random-access memory) section for programming the functions of the blocks. Block 7 is a state sequencer for blocks 11-14 and is described in the preceding article.

Blocks 8 and 9 buffer the Address and Data buses to isolate buses l6 and 17 for blocks 11-14 and block 7. A single ROS (read-only storage) module 6 contains the required microcode and a single RAM module 4 provides temproary storage for the microprocessor and register storage for the user logic. Memory Decode block 5 decodes high-order address lines to decode chip select (CS) for blocks 4 and
6. The Input/Output (I/O) block 10 performs a similar function for I/O devices, such as blocks 2, 3, 7, 11-15. A timer/counter 3 circuit generates a clock signal for the input debounce circuits which are on the user interface side of the SLA partitions. This clock is also used as a prescaler for two other counters within the...