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Semiconductor Device Yield Model for Extended Yields

IP.com Disclosure Number: IPCOM000046179D
Original Publication Date: 1983-Jun-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Stapper, CH: AUTHOR

Abstract

This article describes an easily implemented yield model for calculating partially good and redundancy yields of large memory chips which is suitable for manufacturing control.

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Semiconductor Device Yield Model for Extended Yields

This article describes an easily implemented yield model for calculating partially good and redundancy yields of large memory chips which is suitable for manufacturing control.

The yield model described in a previous article [1] lacks sufficient accuracy to predict the yield of chips containing up to 256K bits.

Yield of perfect chips is given by:

(Image Omitted)

where Yo is the gross yield, Ai is the critical area sensitive to defects of type i, Di is the defect density for defects of type i and ai is a distributional parameter that can be determined with methods described in [2,3]. There are m different defect types indicated by formula (1).

The partially good (1/2, 3/4, 7/8, etc.) yield using the above formulation is:

(Image Omitted)

where there are K good sections out of a total of n, Asi is the critical area for each section sensitive to defects of type i and Aci is the critical area sensitive to chip failures for each defect of type i.

For calculating yield for chips including redundancy the same algorithm as described in [1] is used. This algorithm makes it possible to estimate what fraction Fr of the fixable defects cannot be fixed by redundancy. The yield for perfect plus fixable product can then be determined by:

(Image Omitted)

where Aci is again the critical area for chip failures and Afi is the critical area for fixable failures.

References

1. C. H. STAPPER, A. N. MCLAREN AND M. DRECKMANN, "Yield Mo...