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Non-Volatile, Static Random-Access Memory Cell

IP.com Disclosure Number: IPCOM000046181D
Original Publication Date: 1983-Jun-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Grise, GD: AUTHOR [+4]

Abstract

This normally static random-access memory cell includes a pair of floating-gate memory devices in its load circuit which provides capacitive coupling between the data nodes and the floating gates of the respective depletion-mode load devices to provide the capability of non-volatily storing data in response to a program pulse in the event of a power failure.

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Non-Volatile, Static Random-Access Memory Cell

This normally static random-access memory cell includes a pair of floating- gate memory devices in its load circuit which provides capacitive coupling between the data nodes and the floating gates of the respective depletion-mode load devices to provide the capability of non-volatily storing data in response to a program pulse in the event of a power failure.

The memory cell circuit of Fig. 1 is substantially a 6-device static cell fabricated, for example, in NMOS technology. In normal operation, the floating gates of load devices T1 and T2 are in a neutral charge state such that T1 and T2 act as conventional depletion load devices. A control gate for each load device is connected to a programming line Vp which is at ground.

When a power failure is imminent, the drain supply voltage, normally at about 5 volts, is raised to a programming potential of about 15 volts. Assuming that the volatile data stored is such that circuit node N1 is high (5 volts) and N2 is low (ground), the floating gate in T1 is coupled by the channel and induced gate capacitance of T1 such that its potential with respect to that of the programming gate is greater than a critical programming voltage of the dual electron injector structure formed between the floating gate and the programming gate. Electrons are injected into the floating gate from the programming gate and charge the floating gate negatively. On the other hand, node N2, being at ground, couples substantially less voltage to the floating gate of T2 leaving it in its original neutral state. Data is st...