Browse Prior Art Database

Memory Array Chip With Shared Address Decoders

IP.com Disclosure Number: IPCOM000046182D
Original Publication Date: 1983-Jun-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Kruggel, RH: AUTHOR [+2]

Abstract

In memory chips requiring a plurality of simultaneously selected decoder drivers, circuit density can be improved by providing only a single 1 of 2n decoders, and coupling its outputs to required multiple driver points using second level metallurgy.

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Memory Array Chip With Shared Address Decoders

In memory chips requiring a plurality of simultaneously selected decoder drivers, circuit density can be improved by providing only a single 1 of 2n decoders, and coupling its outputs to required multiple driver points using second level metallurgy.

The figure illustrates this technique for an 8K x 9-bit array organized as 256 words by 288 (32 x 9) bits in which only 32-bit decoder and driver circuits are required. Outputs from the bit drivers are bussed to required locations in the array by the use of a second level of metallurgy (not shown).

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