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Method for Providing Chip Redundancy Using Off-Chip Fuse Pads

IP.com Disclosure Number: IPCOM000046183D
Original Publication Date: 1983-Jun-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Streck, JP: AUTHOR

Abstract

This technique of placing redundancy fuse pads in the wafer kerf area enables the use of current blown fuses without increasing semiconductor chip area.

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Method for Providing Chip Redundancy Using Off-Chip Fuse Pads

This technique of placing redundancy fuse pads in the wafer kerf area enables the use of current blown fuses without increasing semiconductor chip area.

The figure shows a portion of an undiced semiconductor wafer including the edge of a semiconductor chip which requires fuse-controlled redundancy. A fuse, to be selectively blown after chip testing, is formed in a second level of chip metallurgy. Fuse pads, for applying current to the fuse, are physically placed in the kerf area outside of the eventual edge of the diced chip. After testing and any required fuse blowing, the fuse lines are isolated from the edges of the chip by the use of a gross blocking mask which has openings where the fuse lines enter the chip. Final chip passivation and dicing proceed as normal.

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