Browse Prior Art Database

Invalid Address Detection and Recovery Technique

IP.com Disclosure Number: IPCOM000046201D
Original Publication Date: 1983-Jun-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 58K

Publishing Venue

IBM

Related People

Hall, JD: AUTHOR [+3]

Abstract

A recovery aid can be provided to microprocessors which may become "lost" due to invalid jumps or branches caused by line disturbances by sensing the outputs of its several address decoders with each address transmission. The omission of any address decoder output signal provides an indication of error during addressed strobing.

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Invalid Address Detection and Recovery Technique

A recovery aid can be provided to microprocessors which may become "lost" due to invalid jumps or branches caused by line disturbances by sensing the outputs of its several address decoders with each address transmission. The omission of any address decoder output signal provides an indication of error during addressed strobing.

Referring to Fig. 1, an address is transmitted from microprocessor 1 along address bus 2 to each of a plurality of address decoders 3, one of which will normally respond with a valid translation to its assigned bank of memory addresses 4. The output of each decoder is connected to its assigned memory addresses and to a common OR circuit 5 whose output is inverted at 6 as a conditioning input to AND gate 7. The activating input to the gate is a time strobe pulse for address readout.

In operation, each valid address transmitted to a decoder will result in one of the decoders providing an activating signal at its output. That output, transmitted to OR gate 5 and inverted at 6, will result in blocking gate 7, thus suppressing an interrupt at the microprocessor. However, if an address is transmitted along the bus and no decoder responds, the signal level from inverter 6 will condition gate 7 so that an interrupt results during the time strobe.

This interrupt is directed to the microprocessor's highest priority to enable it to execute a recovery routine, preferably with a microprocessor having its own "on chip" read-only storage. Chip internal circuits are usually less susceptible to disruption than circuit board components. A recovery can take such forms as: (1) reinitialize and continue, (2) hang and flag error, or (3) recover via stack check. The requireme...