Browse Prior Art Database

Multiple Interrupt Registration

IP.com Disclosure Number: IPCOM000046202D
Original Publication Date: 1983-Jun-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Hall, JD: AUTHOR [+3]

Abstract

The loss of interrupt requests (IRQs), due to microprocessor status inquiry of pending requests, block out during completion of higher order requests, or priority modification, is avoided by providing input latches settable only at times not coincident with chip select signals.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 63% of the total text.

Page 1 of 2

Multiple Interrupt Registration

The loss of interrupt requests (IRQs), due to microprocessor status inquiry of pending requests, block out during completion of higher order requests, or priority modification, is avoided by providing input latches settable only at times not coincident with chip select signals.

Referring to the figure, any IRQs appear as conditioning inputs to any of the respective input latches l-5. Upon the occurrence of the next address strobe signal (AS), the conditioned latches turn on and their Q outputs activate AND gates 6-l0 and condition intermediate latches ll-l5. Since the Qoutputs of the intermediate latches are on, any IRQ from latches l-5 sets a latch l6-20 to provide a signal to a respective stage of status buffer 2l. Further, when a latch l-5 was set, its output was effective with the termination of the AS pulse through inverter 22 to also set respective intermediate latches ll-l5.

Subsequent signals from the microprocessor at AND gate 23 provide a select signal CS3 for read out of status buffer 2l and, at its conclusion, reset latches l6- 20 through dashed line 24. This arrangement permits any IRQ to be latched into flip-flops l6-20 and transmitted by buffer 2l into the system data bus without loss. Latches l-5 and 6-l0 are reset in successive groups by the termination of their respective IRQs and inverted AS signals.

The logic blocks shown in phantom can be added to the circuit if masking capability is required. The circuits incl...