Browse Prior Art Database

Dense Non-Volatile Mosfet Storage Cells

IP.com Disclosure Number: IPCOM000046252D
Original Publication Date: 1983-Jun-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 26K

Publishing Venue

IBM

Related People

Kotecha, HN: AUTHOR

Abstract

A non-volatile storage cell which is programmed by ion implantation in the gate region of an FET device is disclosed as follows.

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Dense Non-Volatile Mosfet Storage Cells

A non-volatile storage cell which is programmed by ion implantation in the gate region of an FET device is disclosed as follows.

Fig. 1 illustrates a circuit schematic diagram of the invention, and Fig. 2 is a cross-sectional view of the structure of the invention.

In Fig. 1, two serially connected FET devices are between the node Nl and the node N2, and serve to store binary information which is read out by selectively applying enabling signals to the gates of the devices. The first FET device T1 is connected between node 1 and an intervening node 5, and has a gate Gl, and the second FET device T2 is serially connected with the first device T1 between the node 5 and the node N2. The device T2 has the gate electrode G2. The node N1 is maintained at a potential of +10 volts, and the node N2 is connected to a sensing circuit. The channel region of the first FET device T1 can be selectively programmed to either a first binary state or, alternately, to a second binary state by ion-implanting conductivity-enhancing dopant ions therein so as to adjust the threshold voltage of the device. For example, either a first threshold voltage of 5 volts or a second threshold voltage of 10 volts can be alternately programmed into the channel region of the N channel FET device T1 by ion implanting, a selected quantity of an N-type dopant species into the channel region. In a similar manner, the threshold voltage of the serially connected second FET device T2 can also be selectively adjusted to either 5 volts or l0 volts magnitude.

In order to read the binary value stored in the FET device T1, a +5-volt potential is applied to the gate of device T1 and a +10-volt potential is applied to the gate of the FET device T2. When a +10-volt potential is applied to any storage FET device in the array, that device will be guaranteed to be in a conductive state. Therefore, if the threshold voltage of the FET device T1 was originally programmed to be +10 volts, then the +5-volt gate potential on Gl will not be adequate to render the device T1 conductive....