Browse Prior Art Database

System Level Self-Test Method

IP.com Disclosure Number: IPCOM000046260D
Original Publication Date: 1983-Jun-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Peabody, EJ: AUTHOR

Abstract

This scheme allows self-testing of complex logic networks using built- in random number generators and signature analysis.

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System Level Self-Test Method

This scheme allows self-testing of complex logic networks using built- in random number generators and signature analysis.

Logic 10 is provided to inhibit system data inputs to the module and activate a feedback path from shift register latches (SRLs) 12 to the inputs of the combinational logic 14. The numbers scanned into the SRLs 12 are random so that it functions as a random number generation providing a random input to the logic 14. As a result, the module will generate a signature that is based on its logical configuration.

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