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Self-Test of Random-Access Memories

IP.com Disclosure Number: IPCOM000046262D
Original Publication Date: 1983-Jun-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 4 page(s) / 56K

Publishing Venue

IBM

Related People

Bardell, PH: AUTHOR [+2]

Abstract

This scheme provides a minimal length test for the detection of all single and multiple stuck-faults in a random-access memory (RAM). For a RAM with n address bit lines, the algorithm divides each address (ranging from 0 to 2n - 1) by 3 and uses the division remainder (0, 1 or 2) to assign each address to one of 3 groups (G0, G1, and G2).

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Self-Test of Random-Access Memories

This scheme provides a minimal length test for the detection of all single and multiple stuck-faults in a random-access memory (RAM). For a RAM with n address bit lines, the algorithm divides each address (ranging from 0 to 2n - 1) by 3 and uses the division remainder (0, 1 or 2) to assign each address to one of 3 groups (G0, G1, and G2).

Writing and reading the array then proceeds in the following pattern, in which Wr means Write, R means Read, W0 is the word of all 0's, and Wl is the word of all 1's. GROUP STEP G0 G1 G2 1

WrW0 WrW0 2 WrW1 3

RW0 4 WrW1 5

RW0 6 RWl RWl 7 WrW0,

RW0 8 WrW1, RW1

The count-by-3 circuit Fig. 1 can be used to generate in real-time the word addresses for group G0 or G1 or G2, thus obviating the need for the address division step of the algorithm. Figure 2 shows an LSSD shift register latch (SRL) modified to implement the count-by-3 circuit of Fig. 1. In Fig. 2, the signals on the lines marked +Test Mode and -Test Mode are inverses of each other. When not in test mode (-Test Mode at a logical 0), the SRL performs the normal system functions of a system latch using the System Address and System Clock inputs, and scan using the Scan Data input and the Shift A and Shift B clocks.

When in test mode, the circuit of Fig. 2 provides the basic function required to implement the count-by-3 circuit of Fig. 1. Each reproduction of the circuit of Fig. 2 provides one bit position of the array address lines. The low-order address bit, X0, is obtained from the Fig. 2 circuit by tying both the Ci and the Di inputs to a logical 1. Address bit Xl is obtained from the Fig. 2 circuit by connecting the Ci input to the inverse of the X0 address bit and tying input Di to a logical 0. Address bit X2 is obtained from the Fig. 2 circuit by connecting the Ci input to the X0 address bit and the Di input to the X1 address bit. For address bit X3, and for all higher-order address bits, the Ci and Di inputs of the Fig. 2 circuit are connected to the Ci+l and Di+l (respectively) outputs of the next lowest order address bit.

When a memory address register (MAR) is implemented using the described circuitry, testing is initiated by loading into the register, via the normal Scan path, a starting value which is the binary equivalent of decimal 0, l, or 2. (The same effect can be obtained without the Scan operation by providing a controllable set or reset on the X0 and S1 bit register positions and a controllable reset on all higher- order bit positions.) Upon entering test mode, then, the MAR will cycle through the memory addresses by group, beginning with group G0 if 0 was the initial value, with group G1 if l was the initial value, or with group G2 if 2 was the initial value.

The addresses are incremented by 3 on each cycle of the Shift A/Shift B clocks.

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The foregoing description reflects an LSSD double latch design implementation of the MAR. A similar circuit for a single latch design is e...