Browse Prior Art Database

Groove-Trench MIS Capacitor

IP.com Disclosure Number: IPCOM000046325D
Original Publication Date: 1983-Jul-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Lu, NCC: AUTHOR

Abstract

This publication discloses the use of a groove-trench structure formed by dry etching to increase the capacitor electrode area so as to increase the capacitance over that of a planar MIS capacitor with the same die area.

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Groove-Trench MIS Capacitor

This publication discloses the use of a groove-trench structure formed by dry etching to increase the capacitor electrode area so as to increase the capacitance over that of a planar MIS capacitor with the same die area.

Integrated circuits require a high capacitance-density (Hi-C) capacitor. Capacitance can be enhanced by increasing the dielectric constant of the capacitor insulator, decreasing insulator thickness, and increasing electrode area. Described herein is a new capacitor structure which optimizes the utilization of the die area as capacitor electrode and meets the increased requirements of Hi-C capacitors.

Fig. 1 shows the cut-away view of this capacitor structure (the top-plate electrode is not drawn for simplicity). The detailed cross- section view is shown in Fig. 2. It is a Metal (or heavily-doped poly-Si)-Insulator-Semiconductor (MIS) capacitor embedded in a deep trench or groove. The top plate l0 can be metal, silicide, polycide, or heavily-doped poly-Si. The bottom plate 12 can be an N+ layer (or p+ layer) to P-type substrate or vice versa, or even heavily-doped poly- Si. The insulator 14 can be SiO2, Si3N4/SiO2, or any other high dielectric constant material.

The fabrication procedure is described as follows: First, use an etching technique such as reactive ion etching to form a trench. After the N+ layer 12 is diffused or implanted into the P-type substrate, the insulating material 14 is formed on top. Then, a condu...