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REGISTER Renaming for Vector Processors

IP.com Disclosure Number: IPCOM000046335D
Original Publication Date: 1983-Jul-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 16K

Publishing Venue

IBM

Related People

Agerwala, TKM: AUTHOR [+2]

Abstract

Task switching and subroutine linkage overhead is large on a vector processor because a large amount of data must be moved to save and restore vector registers. Specialized hardware and software are described to minimize the number of registers that must be stored. The register assignments made in independently coded subroutines or distinct tasks refer to logical registers. Physical registers are assigned at execution time from a free register pool.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 46% of the total text.

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REGISTER Renaming for Vector Processors

Task switching and subroutine linkage overhead is large on a vector processor because a large amount of data must be moved to save and restore vector registers. Specialized hardware and software are described to minimize the number of registers that must be stored. The register assignments made in independently coded subroutines or distinct tasks refer to logical registers. Physical registers are assigned at execution time from a free register pool.

In order to minimize the amount of memory traffic needed to maintain the integrity of data in vector registers, the following hardware and software modifications are suggested. The register references contained in the compiled code are assumed to refer to logical registers (LRs). The first time a LR is used as a target of either a load or an operation in a three-address architecture, the hardware assigns a physical register (PR) from a free register pool. On subsequent references to this LR, the assigned PR will be used. When the subroutine is exited, all LR to PR assignments made in the subroutine are dropped. In addition, commands exist to explicitly drop a LR to PR assignment and to identify the LR in one routine with the same PR assigned to the LR in the calling routine. This latter allows data to be passed by value in the registers.

The following hardware is needed to support this register renaming. For concreteness, it is assumed that the machine in question has 32 vector general registers (VGRs), 16 vector floating point registers (VFRs), and a mask register for each (VGM and VFM). There is one physical register for each logical register.

1. A Register Assignment Register (RAR) which

contains the LR to PR mapping. The RAR must contain

enough bits to describe this mapping. In our example,

we need 5 bits to assign each of the 32 VGR and VGM and

4 bits to assign each of the 16 VFR and VFM, a total of

448 bits.

2. Four Next Unused Registers (NURs) which contain

the next available register, one for each type ((VGR,

VFR, VGM, VFM) with each 5 bits wide. While the best

method to assign registers is a least recently used

(LRU) algorithm, it is probably too costly to

implement in hardware. The LRU algorithm can be

approximated by assigning the registers in numerical

order modulo the number of registers. Thus, if a

subroutine assigns 5 logical VGRs, physical VGRs from

NUR(VGR) to NUR(VGR)+4 will be used.

3. A Not In Use (NIU) register containing one bit for

every vector register in the machine. If a bit in the

NIU is 1, then the register need not be restored on

return from the subroutine. The bits are set to 0 when

the register is used as a target, and are set to 1 by

the Free Register instruction. The format is

FREE REGISTER LRn,LRm

1

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where all registers between LRn and LRm inclusive will

be freed; i.e., the corresponding bits in NIU will be

set to 1.

It is assumed that the assembler stores a list of the number of each type of register...