Browse Prior Art Database

SRL Arrangement to Minimize Latches in LSSD Design

IP.com Disclosure Number: IPCOM000046364D
Original Publication Date: 1983-Jul-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Hanna, SD: AUTHOR

Abstract

This article describes an arrangement of latches and the use of input ports in system latches to avoid adding latches solely for the purpose of creating a circuit which complies with Level Sensitive Scan Design (LSSD) rules.

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SRL Arrangement to Minimize Latches in LSSD Design

This article describes an arrangement of latches and the use of input ports in system latches to avoid adding latches solely for the purpose of creating a circuit which complies with Level Sensitive Scan Design (LSSD) rules.

It is useful to have logic between stages of a shift register in a pipeline, and if there are an even number of latches on both sides of the logic, no particular problem is presented for LSSD design since there are two latches in each Shift Register Latch (SRL). If there are an odd number of latches on either side of the logic, it would appear that extra components are needed. However, by using an SRL with two system data ports, one data port per latch (L2* SRL), and by connecting ports properly, unnecessary latches can be avoided.

In the figure, logic 10 might be a ripple adder or a comparator, and signals DC1 and DD1 might both be functions of both signals DA2 and DB2. If there are an odd number of latches on both sides of logic 10, latch A and latch C (or latch
D) could be placed in the same L2* SRL, thus avoiding conflict with LSSD rules. If the logic 10 is not a function of several input bits, more flexibility is possible for arranging the input ports, for example, latches A and B could be in the same L2* SRL. Often, all of the latches can be used functionally if the logic is partitioned properly.

One LSSD design rule must be carefully observed: "System signals may be taken from any of t...