Browse Prior Art Database

Memory Refresh Timing

IP.com Disclosure Number: IPCOM000046385D
Original Publication Date: 1983-Jul-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Book, JR: AUTHOR [+2]

Abstract

It is sometimes deisrable to attach a memory having a shorter refresh cycle to a system which is designed for a memory having a larger refresh cycle. For example, one may care to attach a memory having a nominal 2-millisecond refresh cycle to a system designed for a refresh cycle of 6 milliseconds.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 1

Memory Refresh Timing

It is sometimes deisrable to attach a memory having a shorter refresh cycle to a system which is designed for a memory having a larger refresh cycle. For example, one may care to attach a memory having a nominal 2-millisecond refresh cycle to a system designed for a refresh cycle of 6 milliseconds.

A system with a 6-millisecond refresh cycle would generate two pulses to refresh each address. It has been found advantageous to take those pulses when they occur and refresh two memory locations. This results in a memory refresh cycle of 1.5 milliseconds. However, a memory with a nominal refresh cycle of 2 milliseconds will work satisfactorily with a refresh cycle of 1.5 milliseconds, and the circuitry required to do the refresh on a 1.5-millisecond timing is substantially simpler than that which would be required to refresh on the 2-millisecond timing.

Using this technique, no changes are required in the circuitry in the system in order to accommodate the memory with the shorter refresh cycle.

1