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TEST-SITE DESIGN FOR MONITORING CRACKED SiO2

IP.com Disclosure Number: IPCOM000046405D
Original Publication Date: 1983-Jul-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Hopper, GS: AUTHOR [+2]

Abstract

A simple test structure, consisting of many contact pads connected to a silicon substrate and one contact pad connected to a large aluminum- copper plate which is isolated from the silicon substrate by standard SiO2 underlay, provides a test site for monitoring cracked SiO2 handling damage. The structure has more area susceptible to damage than possessed by product chips, and it can be electrically tested easily after exposure to handling impacts.

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TEST-SITE DESIGN FOR MONITORING CRACKED SiO2

A simple test structure, consisting of many contact pads connected to a silicon substrate and one contact pad connected to a large aluminum- copper plate which is isolated from the silicon substrate by standard SiO2 underlay, provides a test site for monitoring cracked SiO2 handling damage. The structure has more area susceptible to damage than possessed by product chips, and it can be electrically tested easily after exposure to handling impacts.

Vertical and horizontal views are shown in Figs. 1 and 2, respectively.

Electrical test can be done in whole wafer form to monitor underlay defects due to photolithography, and in diced (chip) form on standard testers to monitor handling damage. The test program simply measures the current flow from the one contact solder pad (C4) connected to the Al-Cu to all of the other pads in sequence.

Yield and reliability projections for a standard product are made using the ratio of the A1-Cu on the test chip to the area of the Al-Cu on the product chip.

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