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Simultaneous Compare of Multi-Test Pattern Results During Lsi/Vlsi Component Testing

IP.com Disclosure Number: IPCOM000046461D
Original Publication Date: 1983-Jul-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Bansal, JP: AUTHOR

Abstract

In existing testing techniques in which test patterns are cyclically applied to an LSI logic or memory chip device, one pattern at a time, the tester reads the outputs from the chip at each cycle, compares with the expected outputs from the tester's memory, and makes pass/fail decisions. Since the memory cycle time of the tester itself is generally slower than the newer technology LSI chips being tested, the memory cycle time of the tester limits the speed with which the overall test operation can be conducted. Some LSI parts require hundreds of thousands of test patterns to insure their functionality. Hence, reducing the cycle time of each test pattern will result in overall reduction in device test time.

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Simultaneous Compare of Multi-Test Pattern Results During Lsi/Vlsi Component Testing

In existing testing techniques in which test patterns are cyclically applied to an LSI logic or memory chip device, one pattern at a time, the tester reads the outputs from the chip at each cycle, compares with the expected outputs from the tester's memory, and makes pass/fail decisions. Since the memory cycle time of the tester itself is generally slower than the newer technology LSI chips being tested, the memory cycle time of the tester limits the speed with which the overall test operation can be conducted. Some LSI parts require hundreds of thousands of test patterns to insure their functionality. Hence, reducing the cycle time of each test pattern will result in overall reduction in device test time.

The overall test time can be significantly speeded up by the invention shown in the figure. The tester inputs test patterns on input lines l to the device 4 under test and result data is output from the device 4 at the output pads 3. In accordance with the invention, auxiliary high-speed shift registers 2 are provided on the test board of the device 4 under test. The serial input 5 of each shift register is respectively connected to one of the output pads 3 of the device 4 under test. Each shift register 2 stores several cycles-worth of serial data output from its respective pad 3 on the device 4 under test, at the high speed of the chip. Surplus input channels of the tester ar...