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Differential Memory Output Validity Detector

IP.com Disclosure Number: IPCOM000046462D
Original Publication Date: 1983-Jul-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 49K

Publishing Venue

IBM

Related People

DeFilippi, RJ: AUTHOR

Abstract

A circuit is disclosed for providing a separate validity check of the differential sense lines output from a memory chip so as to affirmatively determine whether the difference in potential between the two sense lines output from the memory chip is large enough to be a valid output signal.

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Differential Memory Output Validity Detector

A circuit is disclosed for providing a separate validity check of the differential sense lines output from a memory chip so as to affirmatively determine whether the difference in potential between the two sense lines output from the memory chip is large enough to be a valid output signal.

A differential memory is any memory having two sense lines as the output for each column of RAM (random-access memory) storage cells. In a differential memory, the two sense lines are connected to opposite poles of a differential sense amplifier and a one bit stored at a RAM cell is read out as a plus value on one line and a minus value on the other line, whereas a zero value is read out of a RAM cell with the sense line polarities in reverse order. This is graphically illustrated in Fig. la.

A problem arises when a differential memory becomes de-selected. The memory chip will have both a read/write line and a chip select line. To select the memory for either a read or write operation, the select line is raised. If the chip is not to be selected, the select line is lowered. A problem has been observed when the select line is lowered, that the first and second sense line outputs both rise or fall to the same potential. An example of this is shown in Fig. 1b where even though the memory chip has been de-selected, the output will fall to -50 mv or +50 mv, whereas a valid zero will be -1.6 volts and a valid one state will be +l.6 volts. The -50 mv or +50 mv state, however, will be erroneously interpreted in the same way as a valid minus or plus signal would be interpreted.

The circuit which is described, as follows, avoids this problem by providing a separate validity check of the differential sense lines output from the memory chip to affirmatively determine whether the difference in potential between the two sense lines output from the memory chip are large enough to be a valid output signal.

Fig. 2 illustrates the differential memory validity detection circuit. The input lines X and Y represent the two sense line outputs from the memory. The sense line outputs X and Y are input to the re spective terminals of the differential amplifier l, whose output D0 represents the binary state of the data read out from the RAM.

The sense line outputs X and Y are also input to the respective bases of the PNP transistor 2 and the PNP transistor 3, as shown in Fig. 2. The two transistors have their collectors connected to the...