Browse Prior Art Database

Programmable Drop Option

IP.com Disclosure Number: IPCOM000046463D
Original Publication Date: 1983-Jul-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 52K

Publishing Venue

IBM

Related People

Compeau, GM: AUTHOR [+2]

Abstract

The ability to selectively drop one or both devices in a two-input NAND elementary logic function, for example, can be useful in mask programmable complex logical functions, such as the multiplexer circuit shown in Fig. 7. For example, it would be useful to be able to selectively eliminate device 2 with its Y input and make a short between the source of device l and the ground potential, in order to allow the designer to hardwire program a value of Y equals one. Alternately, it would be useful for the designer to have the ability to eliminate devices 1 and 2 at the mask level in order to hardwire program a value of Y equals zero for the circuit of Fig. 7. This is accomplished by the programmable drop option invention which is described as follows.

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Programmable Drop Option

The ability to selectively drop one or both devices in a two-input NAND elementary logic function, for example, can be useful in mask programmable complex logical functions, such as the multiplexer circuit shown in Fig. 7. For example, it would be useful to be able to selectively eliminate device 2 with its Y input and make a short between the source of device l and the ground potential, in order to allow the designer to hardwire program a value of Y equals one. Alternately, it would be useful for the designer to have the ability to eliminate devices 1 and 2 at the mask level in order to hardwire program a value of Y equals zero for the circuit of Fig. 7. This is accomplished by the programmable drop option invention which is described as follows.

Figs. 1 and 2 illustrate a programmable Y FET device wherein Fig. 1 shows a sequence of three cross-sectional views of the X and Y device as they are fabricated in a gate-masked ion implantation, self-aligned gate FET process, and where Fig. 2 is a circuit schematic diagram of the two devices X and Y in Fig. 1.

Figs. 3 and 4 represent the circuit where devices X and Y are preprogrammed so that Y is identically equal to unity, by eliminating the gate electrode 4 prior to the ion implantation step, thereby providing a continuous diffusion 6 between the FET device X and ground potential.

Figs. 5 and 6 represent the circuit for the circumstance that Y is identically equal to zero. This is carried out by providing a continuous region of recessed oxide 7 where devices X and Y would otherwise have been formed. In this manner, the output node for the circuit will always have an infinite impedance with respect to ground potential corresponding to Y being identically equal to zero.

In Fig. 1, the sequence of processing steps which form the device shown in the schematic of Fig. 2, is as follows. In step A, recessed oxide regions 2 and 2' are formed on the surface of the silicon substrate 1. Thereafter, in step B a thin oxide layer 3 is formed and the polycrystalline silicon gate regions 4 and 4' are deposited on top of the layer 3. Thereafter, in step C the gate- mask ion implantation step is carried out wherein an N-type dopant, such as phosphorus, for example, is ion implanted through the thin oxide layer 3 into...