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Selective GLOBAL Clock Control for a Multi-Processor SYSTEM

IP.com Disclosure Number: IPCOM000046476D
Original Publication Date: 1983-Jul-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 14K

Publishing Venue

IBM

Related People

Stranko, TA: AUTHOR [+2]

Abstract

Activation l) A Central Processor Logic Support System (LSS) receiving a 'modulo 9' (GLOBAL) interrupt. 2) Receiving a hard interrupt from a functional element that has its clock-stopping control masked for continuous operation. 3) The count going to zero during a stop on count/error (SOCE) command to a functional element with LSS ID register bit 9 on. This will generate a global hard stop line which is sent to the System Controller-LSS for control. 4) START, STOP, or SOCE command to a System Controller-LSS with an ID Register Bit (10-15) specification of '100111'B, '101000'B, or '101001'B (LOCAL SYSTEM, REMOTE SYSTEM, TOTAL SYSTEM).

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Selective GLOBAL Clock Control for a Multi-Processor SYSTEM

Activation l) A Central Processor Logic Support System (LSS) receiving a 'modulo 9' (GLOBAL) interrupt. 2) Receiving a hard interrupt from a functional element that has its clock-stopping control masked for continuous operation.
3) The count going to zero during a stop on count/error (SOCE)

command to a functional element with LSS ID register bit 9

on. This will generate a global hard stop line which is sent

to the System Controller-LSS for control. 4) START,

STOP, or SOCE command to a System Controller-LSS with an ID Register Bit (10-15) specification of '100111'B,

'101000'B, or '101001'B (LOCAL SYSTEM, REMOTE SYSTEM, TOTAL

SYSTEM).

General Operation

When one of the activation signals l through 3 is detected within an LSS, the LSS will raise a system hardstop line to the System Controller-LSS. The System Controller-LSS will 'OR' the hardstop from all the books on that power boundary and gate the result with the hardstop bits in the System Controller-LSS Status Register. Depending on the bits, the LSS will either turn on the local or remote stop triggers or ignore the signal. Activating signal 4 will function identically, except that it originates from a command being issued to the System Controller- LSS. The outputs of the stop triggers are sent to the appropriate books where the clocks for the functional elements on that book are stopped (or started, if command generated).

When the global clock stop is activated via an interrupt, an interrupt will be generated on the System Controller-LSS to notify the MSF that a global stop has occurred via an asynchronous LSS stop signal. The response to this interrupt will be a reset interrupt command (RIC) to the System Controller-LSS.

After servicing the System Controller-LSS, the source LSS must be found. The source module is found via the normal error handling routines, and then scanned to correct the problem. Only when the errors have been corrected, can the operations continue. If the interrupt was due to a SOCE command running to completion, a RIC to the source LSS is sufficient for resetting the system hardstop line.

Interrupts

1) 'Module 9' (GLOBAL) hard interrupt. This

interrupt is used

exclusively on the Central Processor book. There

is no mask

bit associated with it, and this interrupt always

signals a

hardstop to the System Contr...